Computer systems, video games, electronic appliances, digital cameras, and myriad other electronic devices include memory for storing data related to the use and operation of the device. A variety of different memory types are utilized in these devices, such as read only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (FLASH), and mass storage such as hard disks and CD-ROM or CD-RW drives. Each memory type has characteristics that better suit that type to particular applications. For example, DRAM is slower than SRAM but is nonetheless utilized as system memory in most computer systems because DRAM is inexpensive and provides high density storage, thus allowing large amounts of data to be stored relatively cheaply. A memory characteristic that often times determines whether a given type of memory is suitable for a given application is the volatile nature of the storage. Both DRAM and SRAM are volatile forms of data storage, which means the memories require power to retain the stored data. In contrast, mass storage devices such as hard disks and CD drives are nonvolatile storage devices, meaning the devices retain data even when power is removed.
Current mass storage devices are relatively inexpensive and high density, providing reliable long term data storage relatively cheap. Such mass storage devices are, however, physically large and contain numerous moving parts, which reduces the reliability of the devices. Moreover, existing mass storage devices are relatively slow, which slows the operation of the computer system or other electronic device containing the mass storage device. As a result, other technologies are being developed to provide long term nonvolatile data storage, and, ideally, such technologies would also be fast and cheap enough for use in system memory as well. The use of FLASH, which provides nonvolatile storage, is increasing popular in many electronic devices such as digital cameras. While FLASH provides nonvolatile storage, FLASH is too slow for use as system memory and the use of FLASH for mass storage is impractical, due in part to the duration for which the FLASH can reliably store data as well as limits on the number of times data can be written to and read from FLASH.
Due to the nature of existing memory technologies, new technologies are being developed to provide high density, high speed, long term nonvolatile data storage. One such technology that offers promise for both long term mass storage and system memory applications is Magneto-Resistive or Magnetic Random Access Memory (MRAM). FIG. 1 is a functional diagram showing a portion of a conventional MRAM array 100 including a plurality of memory cells 102 arranged in rows and columns. Each memory cell 102 is illustrated functionally as a resistor since the memory cell has either a first or a second resistance depending on a magnetic dipole orientation of the cell, as will be explained in more detail below. Each memory cell 102 in a respective row is coupled to a corresponding word line WL, and each memory cell in a respective column is coupled to a corresponding bit line BL. In FIG. 1, the word lines are designated WL1-3 and the bit lines designated BL1-4, and may hereafter be referred to using either these specific designations or generally as word lines WL and bit lines BL. Each of the memory cells 102 stores information magnetically in the form of an orientation of a magnetic dipole of a material forming the memory cell, with a first orientation of the magnetic dipole corresponding to a logic “1” and a second orientation of the magnetic dipole corresponding to a logic “0.” The orientation of the magnetic dipole of each memory cell 102, in turn, determines a resistance of the cell. Accordingly, each memory cell 102 has a first resistance when the magnetic dipole has the first orientation and a second resistance when the magnetic dipole has the second orientation. By sensing the resistance of each memory cell 102, the orientation of the magnetic dipole and thereby the logic state of the data stored in the memory cell 102 can be determined.
To write data to a selected memory cell 102, a row current IROW is applied to the word line WL coupled to the cell and a column current ICOL is applied to the bit line BL coupled to the cell. The row current IROW and column current ICOL generated respective magnetic fields, with only the selected memory cell 102 being subjected to both the magnetic field generated by the row current and the magnetic field generated by the column current. The combination of these magnetic fields applied to the selected memory cell 102 sets the orientation of the magnetic dipole and thereby the resistance of the cell, which writes a data bit corresponding to either a logic 1 or 0 into the cell.
To read data from the MRAM array 100, the resistance of a selected memory cell 102 must be sensed. In one method of sensing the resistance of a selected memory cell 102, a reference voltage VA is applied to the word line WL coupled to the cell, and all other word lines and unselected bit lines BL are coupled to ground. FIG. 1B is a schematic illustrating the equivalent circuit of the MRAM array 100 when the memory cell 102 coupled to the word line WL2 and bit line BL3 is selected. In this situation, the reference voltage VA is applied to the selected word line WL2, and all other word lines WL1, WL3 and unselected bit lines BL1, BL2, BL4 are coupled to ground. The resistance of the selected memory cell 102 is represented by the resistance RSC, which is coupled between word line WL2 and bit line BL3. All unselected memory cells 102 coupled to the selected bit line BL3 are coupled between the bit line BL3 and the unselected word lines WL1, WL3, which are coupled to ground, and these unselected memory cells collectively form a “sneak” resistance RSN. All other unselected memory cells 102 in the array 100 do not affect the equivalent circuit since both ends of these memory cells are coupled to ground via the unselected word lines WL1, WL3, and bit lines BL1, BL2, and BIA, as will be appreciated by those skilled in the art.
In response to the applied reference voltage VA, a read current IR flows through the resistance RSC presented by the selected memory cell 102 and through the sneak resistance RSN to ground. The current IR generates a sense voltage SV on the selected bit line BL3, with the magnitude of this voltage being a function of the magnitude of the resistance RSC of the selected memory cell 102. When the resistance RSC has a larger value, the sense voltage SV on the bit line BL3 will be less than when the resistance RSC has a smaller value. Accordingly, the sense voltage SV has a value indicating the magnitude of the resistance RSC and thus indicating the logic state of the data stored in the selected memory cell 102.
In theory, sensing the resistance value of a selected memory cell 102 to read the logic state of data stored in the cell is simple as just described. In practice, however, reliable sensing is difficult due, in part, to the relatively small change in the resistance of the memory cell 102 between logic states. For example, in a typical MRAM array, each memory cell 102 has a resistance of about 1 Megaohm when the cell stores a logic “1” and a resistance of about 1.1 Megaohms when the cell stores a logic “0.” The differential resistance of the selected memory cell 102 between a logic “1” and a logic “0” is thus only about 100 KΩ or approximately 10%. As a result, the sense voltage SV developed on the bit line BL3 varies by this same amount, making it difficult to reliably detect the sense voltage and determine whether a selected memory cell 102 stores a logic 1 or 0, as will be appreciated by those skilled in the art.
FIG. 2 is a functional block diagram illustrating an existing type of read circuit 200 for sensing the resistance values and thereby reading data from the memory cells 102 in the MRAM array 100 of FIG. 1. In FIG. 2, the same selected memory cell 102 discussed with reference to FIG. 1B is assumed to be selected and thus the equivalent circuit of FIG. 1B is shown as providing sense voltage SV as an input to the read circuit 200. A sense amplifier 202 receives the sense voltage SV from the selected bit line BL3 and generates a pulse clocking signal PCLK which has a frequency of pulses that is a function of the value of the sense voltage SV. A counter 204 receives the PCLK signal and generates a sense count SCNT responsive to each pulse of the PCLK signal. The counter 204 applies the SCNT count to a latch 206 which latches the SCNT count responsive to a latch count signal LC from a reference counter 208. The reference counter 208 is clocked by an applied clock signal CLK and activates the LC signal when an internal count equals a predetermined value, which occurs after a predetermined number of cycles of the CLK signal and thus after a predetermined time T. In this way, the reference counter 208 activates the LC signal to latch the SCNT every T seconds. The counter 204 resets the SCNT count responsive to the LC signal going active. A comparator 210 compares the latched SCNT from the latch 206 to a reference count RCNT and generates a data signal D responsive to this comparison. The RCNT count has a value corresponding to a threshold value for the resistance of the selected memory cell 102. When the SCNT is greater than the RCNT count, the comparator 210 drives the data signal D high, and when the SCNT count is less than the RCNT count the comparator drives the data signal low.
In operation, the resistance RSC corresponding to the selected memory cell 102 and the sneak resistance RSN form a voltage divider, and develop the sense voltage SV on the selected bit line BL3 in response to the voltage VA applied to the selected word line WL2. The sense amplifier 202 generates the PCLK signal having a frequency determined by the value of the sense voltage SV. When the sense voltage SV has a first value corresponding to a first logic state, the PCLK signal has a first number of pulses over a given time period, and when the sense voltage has a second value corresponding to the complementary logic state, the PCLK signal has a second number of pulses over the time period. Initially, the SCNT count generated by the counter 204 the internal count of the reference counter 208 are set to 0 and the LC signal generated by the reference counter is inactive. In response to each pulse of the PCLK signal, the counter 204 increments the SCNT count, and at the same time the reference counter 208 increments the internal count in response to each rising-edge of the CLK signal.
The counter 204 continues incrementing the SCNT count in response to pulses of the PCLK signal. Because the PCLK signal has a frequency determined by the value of the sense voltage SV which, in turn, is determined by the resistance of the selected memory cell 102, the SCNT count is incremented at a rate determined by the resistance of the selected memory cell. At the same time, the reference counter 208 increments the internal count responsive to the CLK signal. The counters 204, 208 continue incrementing their respective counts in response to the PCLK and CLK signals until the internal count generated by the reference counter equals a predetermined value. The reference counter 208 increments the internal count once each cycle of the CLK signal, and thus the internal count equals a predetermined value after a predetermined number of cycles of the CLK signal, which occurs after a predetermined time T. Once the internal count of the reference counter 208 equals the predetermined value, the counter activates the LC signal causing the latch 206 to store the SCNT count at this point. The rate at which the SCNT count is incremented and thus the value of the latched SCNT count depends on the frequency of the PCLK signal which, in turn, depends on the value of the sense voltage SV. In this way, the counter 204 increments the SCNT count responsive to the PCLK signal for the time T, and at this point the value of the SCNT count is stored by the latch 206 and provided to the comparator 210.
The comparator 210 compares the latched SCNT count to the reference count RCNT and drives the signal D either high or low depending on this comparison. When the latched SCNT count has a value that is less than the RCNT count, the sense voltage SV and thus the resistance RSC of the selected memory cell 102 corresponds to a first logic state and the comparator 210 drives the data signal D low, indicating the selected memory cell stores the first logic state. In contrast, when the latched SCNT count is greater than the RCNT count, the sense voltage and resistance RSC of the selected memory cell 102 correspond to the complementary logic state, and the comparator 210 drives the data signal D high, indicating the selected memory cell stores the complementary logic state.
In the read circuit 200, the digital counts SCNT and RCNT are compared to ultimately determine the logic state of data stored in a selected memory cell 102. As a result, the SCNT count must include enough bits and must be incremented at a sufficient rate responsive to the PCLK signal to ensure the generated RCNT has the desired resolution to enable the logic state of the selected memory cell 102 to be reliably sensed, as will be understood by those skilled in the art. Moreover, the circuitry required to form the counter 204 and comparator 210 will be relatively more complicated due to the need to generate and compare all bits in the RCNT and RCNT counts. In addition, with the read circuit 200 the SCNT count corresponding to a give logic state may vary among cells 102 in the array 100 (FIG. 1) due to variations in electrical characteristics among the cells resulting from the physical construction of the array. As a result, the RCNT may ideally need to be varied depending on which cell 102 is being selected, which further complicates the circuitry of the read circuit 200. Although the above description focuses on MRAM technology, the concepts and principles are equally applicable to other types of resistive memory technologies.
There is a need for a simplified method and system for sensing the resistance value of resistive memory cells such as MRAM cells to reliably read data from the cells.